An integrated circuit (IC) can be damaged when subjected to an over-voltage transient that is higher than the design voltage of functional circuit modules inside the integrated circuit. Electrostatic discharge (“ESD”), originating from such sources as a mechanical chip carrier, a plastic chip storage device, or even a human being can generate a voltage that is many times greater than the design voltage of the integrated circuit. For example, the typical human body can supply an electrostatic discharge of 4 kilovolts or more. For integrated circuits that operate at voltages of less than, for example, 5V (volts), an electrostatic discharge of such proportions can be devastating. In order to protect the functional modules in integrated circuits from ESD events, protection cells are utilized, generally between the functional modules and the input/output (“I/O”) terminals (e.g. pads, pins, bumps, etc.) of the integrated circuit. ESD protection circuitry and its layout within semiconductor devices are known from references such as U.S. Pat. Nos. 6,838,775 and 7,446,990.
Integrated circuits (ICs) are also increasing in complexity. The number of devices incorporated within a single IC is greatly increasing and causing the size and complexity of individual ICs to increase. A result of increased component density and improved fabrication technology is the realization of system on chip (SoC) applications. FIG. 1 depicts such an IC or SoC 100 that may include many logic and memory functions within the SoC 100. For example, the IC may include one or more CPU cores, DSP cores, DSP books, memory, control circuitry and analog/mixed signal circuitry modules. These are just a few examples of the types of systems or components that may be integrated into a single IC.
Integrating diverse components within a single IC raises many design challenges. The discrete components may be designed for different entities using different tools or they may follow different design rules. In order for the IC to be useful, the IC must have physical connections to the outside world. Parts of these connections are provided via the IC package. Lower cost wire bond packages are typically used for lower pin count and/or lower performance ICs. Higher cost flip chip packages may, for example be used for higher pin count and/or higher performance ICs.
In FIG. 1, die 102 is configured with an array of flip chip pads or bumps 108. Pads 108 are distributed across die 102, while I/O cells 104 are placed around the edge of die 102 forming what is called the I/O ring. Individual I/O cells 104 are communicatively coupled to individual bumps 108. I/O cells may be of various types, including, for example, signal, clock power or ground. The core region of die 102 contains multiple functional modules 110, which are communicatively coupled to the I/O cells. The I/O cells typically contain ESD protection elements to help prevent damage of the fragile I/O circuitry during an ESD event. In case of digital I/O applications, the digital I/O circuitry is typically contained within the I/O cells together with the ESD protection elements. In case of an analog I/O application, the analog I/O circuitry may be contained inside a functional module in the core region of the die and the primary function of the I/O cells 104 may be housing the ESD protection elements.
Traditional ICs fall into two general categories, core-limited and I/O limited. A core-limited chip is one where the size of the chip is dependent on the amount of logic circuitry (i.e. functional modules 110) contained therein. The perimeter of the chip, in this case, is sufficient to support all the required I/O cells 104, surrounding the core. An I/O-limited IC's size, on the other hand, is dictated by the number of I/O cells 104 on the die's perimeter, wherein cells are as close as possible to each other, consistent with the IC's design rules and packaging rules. Thus I/O limited IC's often contain wasted open space within a die.
Advances in device density within the core have made it possible to reduce the core size of IC devices. However, reduced I/O cell pitch (the pitch is typically defined as the repeat distance between adjacent I/O cells) has been harder to achieve. Therefore, conventional IC designs that are I/O intensive tend to have a die size significantly greater than that of the core.